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DM9000AEP 在KEIL RL-NET下的驱动程序,从u-boot移植而来。
#include <Net_Config.h> #include <stdlib.h> #include "dm9000a.h" #define DM9000_IO 0 #define DM9000_DATA 1 extern U8 own_hw_adr[]; extern int gettime(void); /* DM9000 network board routine ---------------------------- */ static unsigned char DM9000_ior(unsigned char reg) { unsigned char d; DM9000_outb(reg, DM9000_IO); d = DM9000_inb(DM9000_DATA); return d; } static void DM9000_iow(unsigned char reg, unsigned char value) { DM9000_outb(reg, DM9000_IO); DM9000_outb(value, DM9000_DATA); } void udelay(unsigned long n) { for (n *= 5; n != 0; n--) { __nop(); } } /* Search DM9000 board, allocate space and register it */ int dm9000_probe(void) { int id_val; id_val = DM9000_ior(DM9000_VIDL); id_val |= DM9000_ior(DM9000_VIDH) << 8; id_val |= DM9000_ior(DM9000_PIDL) << 16; id_val |= DM9000_ior(DM9000_PIDH) << 24; if (id_val == DM9000_ID) { return 0; } else { return -1; } } /* Write a word to phyxcer */ void dm9000_phy_write(int reg, unsigned short value) { /* Fill the phyxcer register into REG_0C */ DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); /* Fill the written data into REG_0D & REG_0E */ DM9000_iow(DM9000_EPDRL, (value & 0xff)); DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff)); DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */ udelay(500); /* Wait write complete */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */ } /* Read a word from phyxcer */ unsigned short dm9000_phy_read(int reg) { unsigned short val; /* Fill the phyxcer register into REG_0C */ DM9000_iow(DM9000_EPAR, DM9000_PHY | reg); DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */ udelay(100); /* Wait read complete */ DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */ val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL); return val; } /* General Purpose dm9000 reset routine */ static void dm9000_reset(void) { /* Reset DM9000, see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */ /* DEBUG: Make all GPIO0 outputs, all others inputs */ DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT); /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */ DM9000_iow(DM9000_GPR, 0); /* Step 2: Software reset */ DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); do { udelay(25); /* Wait at least 20 us */ } while (DM9000_ior(DM9000_NCR) & 1); DM9000_iow(DM9000_NCR, 0); DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */ do { udelay(25); /* Wait at least 20 us */ } while (DM9000_ior(DM9000_NCR) & 1); /* Check whether the ethernet controller is present */ while (dm9000_probe() < 0); } /* Initialize dm9000 board */ void init_ethernet(void) { int i, oft, lnk; /* RESET device */ dm9000_reset(); /* Program operating register, only internal phy supported */ DM9000_iow(DM9000_NCR, 0x0); /* TX Polling clear */ DM9000_iow(DM9000_TCR, 0); /* Less 3Kb, 200us */ DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US); /* Flow Control : High/Low Water */ DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* SH FIXME: This looks strange! Flow Control */ DM9000_iow(DM9000_FCR, 0x0); /* Special Mode */ DM9000_iow(DM9000_SMCR, 0); /* clear TX status */ DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* Clear interrupt status */ DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); /* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) DM9000_iow(oft, own_hw_adr[i]); for (i = 0, oft = 0x16; i < 8; i++, oft++) DM9000_iow(oft, 0xff); /* Activate DM9000 */ /* RX enable */ DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_ALL | RCR_RXEN); /* Enable TX/RX interrupt mask */ DM9000_iow(DM9000_IMR, IMR_PAR); i = 0; while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */ udelay(1000); i++; if (i == 10000) { return; } } } /* Received a packet and pass to upper layer */ void poll_ethernet(void) { unsigned char rxbyte; unsigned short rxstatus, rxlen; OS_FRAME *frame = NULL; /* There is _at least_ 1 package in the fifo, read them all */ for (;;) { DM9000_ior(DM9000_MRCMDX); /* Dummy read */ /* Get most updated data, only look at bits 0:1, See application notes DM9000 */ rxbyte = DM9000_inb(DM9000_DATA); /* Status check: this byte must be 0 or 1 */ if (rxbyte > DM9000_PKT_RDY) { init_ethernet(); return; } if (rxbyte != DM9000_PKT_RDY) return; /* No packet received, ignore */ /* A packet ready now & Get status/length */ DM9000_outb(DM9000_MRCMD, DM9000_IO); /* Read packet status */ rxstatus = DM9000_inb(DM9000_DATA); rxstatus += DM9000_inb(DM9000_DATA) << 8; if (rxstatus & 0xBF00 == 0) return; /* Read packet length */ rxlen = DM9000_inb(DM9000_DATA); rxlen += DM9000_inb(DM9000_DATA) << 8; if (rxlen > DM9000_PKT_MAX) { init_ethernet(); return; } /* Move data from DM9000 */ /* Read received packet from RX SRAM */ frame = alloc_mem(rxlen); if (frame != NULL) { DM9000_ReadData(frame->data, frame->length); put_in_queue(frame); } } } /* Hardware start transmission. Send a packet to media from the upper layer. */ void send_frame(OS_FRAME *frame) { /* Move data to DM9000 TX RAM */ DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */ /* push the data to the TX-fifo */ DM9000_WriteData(frame->data, frame->length); /* Set TX length to DM9000 */ DM9000_iow(DM9000_TXPLL, frame->length & 0xff); DM9000_iow(DM9000_TXPLH, (frame->length >> 8) & 0xff); /* Issue TX polling command */ DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ }
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